6 version taint_licensecontents std_mudd.db 2000.05-1library_compiler_versiondesigns operations processors data_classes library_types implementations std_muddtypeunique_cell_prefixunique_net_prefixunique_cell_numberunique_net_number ports references netlist_cells netlist_nets graphics_viewaliases constraintstypesdesign_instancesstd_inv directionA capacitance? pin_used_in_function! pin_number" pin_class# pin_sense$Y%function&A'@'timing(intrinsic_rise)intrinsic_fall* slope_rise+ slope_fall,rise_resistance-fall_resistance. timing_sense/ timing_type0 related_pins>\>>a=qA 1series_parallel2pin_function_class3a1 4pin_function_id5Ia1.0@6 log_attach%7 member_type8members@9 esp_func_id: bag_contents;a' <a=area?@> equal_ports ?equalbag@@opposite ?@ A syn_libraryB function_id5Cfunction_class3D cmog_class3Eebst_processedFnumber_of_pinsGlibgen_usage_classH insert&remove I std_nand2 ?JB?$K(A B)'@?>> ;=2 ?>> ;=2La2 MIa2.0@ @N (a)'+(b)'Ob <@MLLHPstd_nor2?J?$Q(A+B)'@? >>=qA ? >>=qA L Ra2.2@ @!S (a)'*(b)'"O#<@RLLH$T std_nand3%?&J?'UC?($V(A B C)'@)?&ff>p>|=h%*?&ff>p>|=h&+?&ff>p>|=h'Wa3 XIa3.0@,-%.&/'@0Y(a)'+(b)'+(c)'1<'2Zc%3O&@XWWH4[std_nor35?6J?7U?8$\(A+B+C)'@9?O\)>>9=qA 5:?O\)>>9=qA 6;?O\)>>9=qA 7W ]a3.3@<=5>6?7@@^(a)'*(b)'*(c)'AZ7BO6C<5@]WWHD_ std_latchE`D?@F>>ɀɀɀɀGaG? bmin_pulse_width_high? cmin_pulse_width_low? dforce epp_sensefpin_used_in_input_mapH>>ɀɀɀɀG  GIgQhIQi internal_nodeg@J?c ?\(>L=GK?c ?\(>L=Ejeq_op k1_lsequential_outputmevaluation_order@n input_bagLM`orelationp unatenessqactiveNar ebst_data_id@@s seq_modelOhtsecond_variable_nameuIQNvenableawdata_in`@x ebst_modelPy statetablezinputs{ D G |nodes} Q QN ~tableB - L : - - : N N, H/L H : - - : H/L L/H@ state_model  is_a_latch async_force_01 async_force_10 flip_flop_type___a2.1(0,1)_a2.0(0,1)_:1_unknown@specific_to_genericQUnR`SaTgU expand_refreference_ports **FFGEN**V next_stateW clocked_onXforce_00Yforce_01Zforce_10[force_11\g]QNis_a_generic_flip_flop^*GEN*0_z@` logdb_gena*GEN*1bz2@cd*GEN*2ez3@fg*GEN*3hz4@ijk<lmOkmn*GEN*4oz5@pqrZstdrtu*GEN*5vz6@wx cell_pinscell_refU1yref_portVzW{X|Y}Z~[\]U_^baedhkmgortnvunet_connectionsn1Tgennameyz{|`RaS}~  logdb_ref_cnt@generic_to_specific rise_arrival fall_arrival rise_drive fall_driveloadgz7@efgh@ log_dc_attachuvwxz9@mop@y3b1c1_D`agz11@d1U3U5U6switching_activitystatic_probability`ag basic_ff_function_id@specific_to_seqgen`ag **SEQGEN**clearpresetwvg synch_clear synch_preset synch_toggle synch_enableis_a_generic_seqz12@z13@z14@z15@z16@e1z17@f1*GEN*6z18@*GEN*7z19@*GEN*8z20@*GEN*9z21@clear_preset_var1clear_preset_var2wvw`va @seqgen_to_specific wvgz22@g1z24@h1_D`agz26@i1w`vag  ebst_validHdefault_inout_pin_cap?default_inout_pin_fall_resdefault_inout_pin_rise_resdefault_input_pin_cap?default_intrinsic_fall?default_intrinsic_rise?default_output_pin_capdefault_output_pin_fall_res default_output_pin_rise_res default_slope_fall default_slope_rise default_fanout_load? k_process_drive_fall?k_process_drive_rise?k_process_intrinsic_fall?k_process_intrinsic_rise?k_process_pin_capk_process_slope_fall?k_process_slope_rise?k_process_wire_capk_process_wire_res?k_temp_drive_fall;r{k_temp_drive_rise;r{k_temp_intrinsic_fall;r{k_temp_intrinsic_rise;r{k_temp_pin_capk_temp_slope_fallk_temp_slope_risek_temp_wire_capk_temp_wire_resk_volt_drive_fall k_volt_drive_rise!k_volt_intrinsic_fall"k_volt_intrinsic_rise#k_volt_pin_cap$k_volt_slope_fall%k_volt_slope_rise&k_volt_wire_cap'k_volt_wire_res( voltage_unit) current_unit*pulling_resistance_unit+capacitive_load_units=, nom_process?-nom_temperatureA. nom_voltage@@pvttWCCOM process?  temperatureB voltage@  tree_typeworst_case_treeWCIND ? B @ WCMIL ? B @ BCCOM ? @ best_case_treeBCIND ? @ BCMIL ? \ @ @ wire_load05x05 resistance?=slope>>vɂ@ fanout_lengthfanoutlength>Ǯ10x10?>;d@?20x20?? 1@?\(30x30??H1'@?3340x40??`@?3350x50??m@?ff60x60?? J@?ٙ70x70??-@?ff80x80??˅@?ff90x90??녂@?33/k_process_nochange_fall0slew_lower_threshold_pct_riseA1k_process_removal_fall2k_process_min_pulse_width_low3k_volt_drive_current4slew_upper_threshold_pct_riseB5slew_derate_from_library?6k_temp_skew_rise7k_volt_min_pulse_width_high8k_volt_setup_fall9k_volt_min_pulse_width_low:k_temp_hold_fall;k_temp_nochange_rise<k_volt_skew_rise=k_process_internal_power>k_volt_hold_fall?k_volt_internal_power@k_process_skew_fallAk_process_nochange_riseBk_process_removal_riseCk_temp_min_periodDk_temp_removal_fallEk_volt_setup_riseFk_temp_hold_riseGk_volt_recovery_fallHinput_threshold_pct_fallBHIk_volt_hold_riseJk_process_pin_fall_capKk_process_skew_riseLk_temp_min_pulse_width_lowMk_temp_internal_powerNk_process_recovery_riseOk_temp_removal_risePk_process_hold_fallQk_temp_drive_currentRk_temp_skew_fallSk_process_cell_leakage_powerTk_temp_setup_fallUoutput_threshold_pct_fallBHVk_volt_recovery_riseWk_temp_nochange_fallXinput_threshold_pct_riseBHYk_volt_removal_fallZk_process_hold_rise[k_process_min_period\k_volt_cell_leakage_power]k_temp_min_pulse_width_high^k_temp_setup_rise_k_volt_nochange_fall`output_threshold_pct_riseBHak_temp_recovery_fallbk_volt_removal_riseck_process_recovery_falldk_volt_nochange_riseek_process_setup_fallfk_temp_recovery_risegk_volt_min_periodhk_process_pin_rise_capislew_lower_threshold_pct_fallAjslew_upper_threshold_pct_fallBkk_temp_cell_leakage_powerlk_process_setup_risemk_volt_skew_fallnk_process_drive_currentok_process_min_pulse_width_highpvalid_porosityqtime_unit_namensr time_scalesin_place_swap_modet degenerateu degeneratedvEwebst_data_arrayx"esax_library_leak_power_unit_scaleyABOIa1.0Ia2.0Ia3.0     a1.0a2.2a3.3library_modified_dateTue Jan 09 17:45:43 2001 lib_gen>Library Compiler Version 2000.05-1 : Tue Jan 09 17:45:54 2001 uidb_version_attribute