The IEEE Journal of Solid-State Circuits is
abbreviated as JSSC because it is cited heavily. Most of the references in IEEE publications
since 1988 can be obtained from ieeexplore.ieee.org. They are available to subscribing
institutions, to individuals with a personal subscription, or for a fee. This
page contains experimental links directly to a few of the papers.
[Acken83] J. Acken, "Testing for
bridging faults (shorts) in CMOS circuits," Proc. Design Automation
Conf., 1983, pp. 717-718.
[Acosta95] A. Acosta, M. Valencia, A.
Barriga, M. Bellido, and J. Huertas, "SODS: A new CMOS differential-type
structure," JSSC, vol. 30, no. 7, July 1995, pp. 835-838.
[Afghahi90] M. Afghahi and C. Svensson,
"A unified single-phase clocking scheme for VLSI systems," JSSC,
vol. 25, no. 1, Feb. 1990, pp. 225-233.
[Allam00] M. Allam, M. Anis, and M.
Elmasry, "High-speed dynamic logic styles for scaled-down CMOS and MTCMOS
technologies," Proc. Intl. Symp. Low Power Electronics and Design,
2000, pp. 155-160.
[Allam01] M. Allam and M. Elmasry,
"Dynamic current mode logic (DyCML): a new low-power high-performance
logic style," JSSC, vol. 36, no. 3, March 2001, pp. 550-558.
[Alvandpour02] A. Alvandpour, R.
Krishnamurthy, K. Soumyanath, and S. Borkar, "A sub-130-nm conditional
keeper technique," JSSC, vol. 37, no. 5, May 2002, pp. 633-638.
[Amrutur00] B. Amrutur and M. Horowitz,
"Speed and power scaling of SRAM's," JSSC, vol. 35, no. 2,
Feb. 2000, pp. 175-185.
[Amrutur01] B. Amrutur and M. Horowitz,
"Fast low-power decoders for RAMs," JSSC, vol. 36, no. 10,
Oct. 2001, pp. 1506-1515.
[Amrutur98] B. Amrutur and M. Horowitz,
"A replica technique for wordline and sense control in low-power
SRAM's," JSSC, vol. 33, no. 8, Aug. 1998, pp. 1208-1219.
[Anastasakis02] D. Anastaskasis, R. Damiano,
H. Ma, and T. Stanion, “A practical and efficient method for compare-point
matching,” Proc. Design Automation Conf., June 2002, pp. 305-310.
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E. Berta, "The core clock system on the next generation Itanium
microprocessor," Proc. IEEE Intl. Solid-State Circuits Conf., Feb.
2002, pp. 146-147, 453.
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pp. 50-52.
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"Impact of technology scaling on metastability performance of CMOS
synchronizing latches," Proc. Intl. Conf. VLSI Design, 2002, pp.
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1.4-V 25-MS/s pipelined ADC using opamp-reset switching technique,” JSSC,
vol. 38, no. 8, Aug. 2003, pp. 1401-1404.
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“Behavior analysis of CMOS D flip-flops,” JSSC, vol. 24, no. 5, Oct.
1989, pp. 1454-1458.
[Chappell91] T. Chappell, B. Chappell, S.
Schuster, J. Allan, S. Klepner, R. Joshi, and R. Franch, "A 2-ns cycle,
3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture," JSSC,
vol. 26, no. 11, Nov. 1991, pp. 1577-1585.
[Cheng00y] Y. Cheng, C. Tsai, C. Teng,
and S. Kang, Electrothermal Analysis of VLSI Systems,
[Cheng99] Y. Cheng and C. Hu, MOSFET
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P. Li, and P. Yang,” Multilevel metal capacitance models for CAD design
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[Childs84] R. Childs, J. Crawford, D.
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[Chillarige03] Y. Chillarige, S. Dubey, S.
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using Propagate (P), Generate (G), and Kill (K) signals in push-pull style for
a next generation UltraSparc microprocessor," Proc. IEEE Custom
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[Chinnery02] D. Chinnery and K. Keutzer, Closing
the Gap Between ASIC and Custom: Tools and techniques
for high-performance ASIC design,
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20 Msample/s, 35mW pipeline A/D converter,” JSSC, vol. 30, no. 3, March
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[Choi97] J. Choi, L. Jang, S. Jung
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partial product tree compression," JSSC, vol. 32, no. 3, March
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[Choudhury97] M. Choudhury and J. Miller,
"A 300 MHz CMOS microprocessor with multi-media technology," Proc.
IEEE Intl. Solid-State Circuits Conf., 1997, pp. 170-171.
[Chu86] K. Chu and D. Pulfrey,
“Design procedures for diffential cascode voltage switch circuits,” JSSC,
vol. SC-21, no. 6, Dec. 1986, pp. 1082-1087.
[Chu87] K. Chu and D. Pulfrey,
"A comparison of CMOS circuit techniques: differential cascode voltage
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[Ciletti99] M. Ciletti, Modeling,
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[Colwell95] R. Colwell and R. Steck,
"A 0.6 mm
BiCMOS processor with dynamic execution," Proc. IEEE Solid-State
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